`include "defines.v"
module id_ex(
	input wire clk,
	input wire rst,
	input wire[31:0] id_reg1,
	input wire[31:0] id_reg2,
	input wire[4:0] id_reg3_addr,
	input wire id_reg3_write,
	input wire[`AluOpWidth-1:0] id_alu_op,
	// input wire[`AluSelWidth-1:0] id_alu_sel,
	output reg[31:0] ex_reg1,
	output reg[31:0] ex_reg2,
	output reg[4:0] ex_reg3_addr,
	output reg ex_reg3_write,
	output reg[`AluOpWidth-1:0] ex_alu_op
	// output reg[`AluSelWidth-1:0] ex_alu_sel
	
);
	always@(posedge clk) 
		if(rst == `RstEnable)
		begin
			ex_reg1 <= `ZeroWord;
			ex_reg2 <= `ZeroWord;
			ex_reg3_addr <= 5'b00000;
			ex_reg3_write <= `WriteDisable;
			ex_alu_op <= `ALU_NOP_OP;
			// ex_alu_sel <= `ALU_RES_NOP;
		end
		else
		begin
			ex_reg1 <= id_reg1;
			ex_reg2 <= id_reg2;
			ex_reg3_addr <= id_reg3_addr;
			ex_reg3_write <= id_reg3_write;
			ex_alu_op <= id_alu_op;
			// ex_alu_sel <= id_alu_sel;
		end
endmodule